The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

May. 16, 2013
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Parameshwarappa Anand Kumar Savanth, Cambridge, GB;

James Edward Myers, Cambridge, GB;

David Walter Flynn, Cambridge, GB;

Bal S. Sandhu, San Jose, CA (US);

Assignee:

ARM Limited, Cambridge, GB;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); G01R 19/00 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
G01R 19/0084 (2013.01); H02M 3/07 (2013.01); Y02B 70/16 (2013.01);
Abstract

An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.


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