The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Jan. 23, 2015
Applicant:

Covidien Lp, Mansfield, MA (US);

Inventors:

Wayne L. Moul, Loveland, CO (US);

Robert J. Behnke, II, Erie, CO (US);

Scott E. M. Frushour, Boulder, CO (US);

Jeffrey L. Jensen, Boulder, CO (US);

Assignee:

Covidien LP, Mansfield, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H01P 3/08 (2006.01); H01P 11/00 (2006.01); H05K 1/18 (2006.01); H05K 3/46 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0218 (2013.01); H01P 3/088 (2013.01); H01P 11/003 (2013.01); H05K 1/0243 (2013.01); H05K 1/0298 (2013.01); H05K 1/183 (2013.01); H05K 1/025 (2013.01); H05K 1/0225 (2013.01); H05K 1/0231 (2013.01); H05K 1/186 (2013.01); H05K 3/4611 (2013.01); H05K 2201/066 (2013.01); H05K 2201/0715 (2013.01); H05K 2201/0723 (2013.01); H05K 2201/0969 (2013.01); H05K 2203/063 (2013.01);
Abstract

A printed circuit board includes a first layer stack and a second layer stack coupled to the first layer stack. The first layer stack includes a first electrically-insulating layer, a first electrically-conductive layer, and a cut-out area defining a void that extends therethrough. The first electrically-insulating layer includes a first surface and an opposite second surface. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second layer stack includes a second electrically-insulating layer. The second electrically-insulating layer includes a first surface and an opposite second surface. One or more electrically-conductive traces are disposed on the first surface of the second electrically-insulating layer. The printed circuit board further includes a device at least partially disposed within the cut-out area. The device is electrically-coupled to one or more of the one or more electrically-conductive traces disposed on the first surface of the second electrically-insulating layer.


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