The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Jun. 05, 2012
Applicants:

Toshiharu Sakai, Suita, JP;

Ryoji Azumi, Sakai, JP;

Kiyomasa Nishisaka, Sanda, JP;

Daisuke Hirata, Ibaraki, JP;

Hiroyuki Kitajima, Oyama, JP;

Inventors:

Toshiharu Sakai, Suita, JP;

Ryoji Azumi, Sakai, JP;

Kiyomasa Nishisaka, Sanda, JP;

Daisuke Hirata, Ibaraki, JP;

Hiroyuki Kitajima, Oyama, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04Q 11/04 (2006.01); G06F 11/07 (2006.01); H04L 15/00 (2006.01); H04L 1/00 (2006.01); H03M 13/15 (2006.01); H03M 13/00 (2006.01);
U.S. Cl.
CPC ...
H04L 1/0052 (2013.01); H03M 13/1515 (2013.01); H03M 13/6561 (2013.01);
Abstract

An error correction processing circuit, includes: a division circuit that divides input data into a plurality of pieces of a predetermined data length; a plurality of operation circuits that are provided in parallel, and that perform operations of error correction for the plurality of pieces of data divided by the division circuit, respectively; a multiplexing circuit that multiplexes the plurality of pieces of data for which the operations have been performed by the plurality of operation circuits; and an output circuit that outputs the data multiplexed by the multiplexing circuit.


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