The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Jan. 28, 2014
Applicant:

Google Inc., Mountain View, CA (US);

Inventors:

Robert Felderman, Portola Valley, CA (US);

Abdul Kabbani, Los Gatos, CA (US);

Assignee:

Google Inc., Mountain View, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04J 14/00 (2006.01); H04B 10/27 (2013.01); H04L 12/751 (2013.01); H04L 12/933 (2013.01); H04Q 11/00 (2006.01); H04L 12/24 (2006.01); H04L 12/947 (2013.01);
U.S. Cl.
CPC ...
H04B 10/27 (2013.01); H04L 41/12 (2013.01); H04L 45/02 (2013.01); H04L 49/15 (2013.01); H04L 49/25 (2013.01); H04Q 11/0071 (2013.01); H04Q 2011/009 (2013.01); H04Q 2011/0052 (2013.01);
Abstract

The present disclosure describes systems and methods for reconfiguring the links made by a plurality of optical circuit switches between the nodes of the first layer and the nodes of the second layer that reduces the throughput loss when the network transitions form a first logical topology to a second logical topology. More particularly, the first logical topology is realized by a specific physical topology, while the second logical topology may be realized by one or more physical topologies. The disclosure describes a method for selecting a second physical topology from the one or more physical topologies that will realize the second logical topology while reducing the number of links within each of the optical circuit switches that must be reconfigured (i.e, disconnected from their present ports and reconnected to new ports within the optical circuit switch) to transition from the first to second logical topology.


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