The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
Dec. 27, 2013
Applicants:
Gaurav Gupta, Noida, IN;
Shiva Belwal, Noida, IN;
Ashish Goel, Noida, IN;
Inventors:
Assignee:
FREESCALE SEMICONDUCTOR, INC, Austin, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/356 (2006.01); H03K 19/173 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 19/1733 (2013.01); H03K 3/037 (2013.01); H03K 3/35606 (2013.01); H03K 3/356026 (2013.01); H03K 3/356078 (2013.01); H03K 19/1736 (2013.01);
Abstract
A configurable flip-flop circuit has modifiable connections between its circuit elements that allow it to be modified for primary and secondary uses. For example, the flip-flop circuit can be modified to provide secondary functions of NOR and NAND gates during an implementation of an ECO. At other times, the flip-flop circuit can be used to deliver normal flip-flop functionality. A configurable latch circuit is provided that can be modified to provide an output signal or an inverted output signal. A scan circuit is provided that can provide the functionality of a multiplexer.