The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Aug. 01, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Foong Tek Chan, Kuala Lumpur, MY;

Xiabao Wang, Cupertino, CA (US);

Khai Nguyen, San Jose, CA (US);

Chiakang Sung, Milpitas, CA (US);

Ket Chiew Sia, Bayan Lepas, MY;

Boon Jin Ang, Butterworth, MY;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01);
Abstract

A high speed IO buffer is disclosed. The high speed IO buffer includes a first P-type metal oxide semiconductor (PMOS) transistor coupled to an IO voltage source. The high speed IO buffer also includes a first N-type metal oxide semiconductor (NMOS) transistor coupled to a ground source, a second PMOS transistor coupled to the first PMOS transistor and a pad and a second NMOS transistor coupled to the first NMOS transistor and the pad. The first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are arranged in a cascoded arrangement.


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