The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
Oct. 02, 2013
Applicant:
Altera Corporation, San Jose, CA (US);
Inventors:
Philip Pan, Fremont, CA (US);
Chiakang Sung, Milpitas, CA (US);
Joseph Huang, San Jose, CA (US);
Yan Chong, Mountain View, CA (US);
Bonnie I. Wang, Cupertino, CA (US);
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H01L 25/00 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017581 (2013.01); H03K 19/17744 (2013.01);
Abstract
Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.