The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Nov. 22, 2013
Applicant:

Stanley Electric Co., Ltd., Tokyo, JP;

Inventors:

Shuichi Ajiki, Tokyo, JP;

Yasuyuki Kawakami, Tokyo, JP;

Tsutomu Akagi, Tokyo, JP;

Mitsunori Harada, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/18 (2006.01); H01L 33/50 (2010.01); H01L 25/075 (2006.01); H01L 27/15 (2006.01); F21K 99/00 (2010.01);
U.S. Cl.
CPC ...
H01L 33/50 (2013.01); H01L 25/0753 (2013.01); H01L 27/15 (2013.01); F21K 9/00 (2013.01); H01L 33/505 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A light emitting apparatus with a combination of a plurality of LED chips and a phosphor layer is provided and can be configured to significantly reduce variations in chromaticity and luminance. The plurality of semiconductor light emitting devices (LED chips) are disposed with a gap therebetween, and the phosphor layer is formed on the upper surface thereof to bridge over the gaps between the LED chips. The phosphor layer may be uniform in thickness, but can be less in thickness over the gaps between the LED chips than on the upper surface of the LED chips. The phosphor layer can be continuously formed on the upper surface of the array of the chips with no phosphor layer present in between the chips. This configuration allows for reducing variations in luminance and chromaticity which may result from the gaps or the phosphor layer present in between the gaps.


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