The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Sep. 16, 2014
Applicant:

AU Optronics Corporation, Hsin-Chu, TW;

Inventors:

Wan-Heng Chang, Hsin-Chu, TW;

Hsiao-Wei Cheng, Hsin-Chu, TW;

Shih-Chyuan Fan Jiang, Hsin-Chu, TW;

Assignee:

AU OPTRONICS CORPORATION, Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1222 (2013.01); H01L 29/786 (2013.01); H01L 27/1218 (2013.01);
Abstract

An array substrate includes a scan line, a data line, a thin film transistor, a first transparent electrode, a passivation layer, and a second transparent electrode. The scan line and the data line interlace to define a pixel region. The gate dielectric layer of the thin film transistor overlaps the scan line and the data line and extends to cover the pixel region. The gate dielectric layer has a first region, a second region, and a third region. The first region corresponds to the semiconductor layer of the thin film transistor. The second region connects the first region and the third region. The thickness of the second region is different from that of the third region. The first transparent electrode covers the gate dielectric layer in the pixel region. The passivation layer covers the thin film transistor and the first transparent electrode. The second transparent electrode covers the passivation layer.


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