The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Sep. 07, 2012
Applicant:

Nam-jae Lee, Gyeonggi-do, KR;

Inventor:

Nam-Jae Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 21/76 (2006.01); H01L 21/3205 (2006.01); H01L 21/4763 (2006.01); H01L 27/115 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11546 (2013.01); H01L 27/0629 (2013.01); H01L 27/11529 (2013.01);
Abstract

A method for fabricating a nonvolatile memory device includes forming a first insulation layer and a first conductive layer on a substrate including a first region and a second region, forming a first isolation trench in the first region by etching the first conductive layer, the first insulation layer, and the substrate, forming a first isolation layer filled in the first isolation trench, forming a second insulation layer and a conductive capping layer, etching the capping layer and the second insulation layer, forming a second conductive layer, and forming first gate patterns by etching the second conductive layer, the capping layer, the second insulation layer, the first conductive layer, and the first insulation layer of the first region, and forming a second isolation trench in the second region by etching the second conductive layer, the first conductive layer, the first insulation layer, and the substrate.


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