The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Jun. 26, 2012
Applicants:

Hyun-woo Chung, Seoul, KR;

Jiyoung Kim, Yongin-si, KR;

Yongchul OH, Suwon-si, KR;

Sungkwan Choi, Hwaseong-si, KR;

Yoosang Hwang, Suwon-si, KR;

Inventors:

Hyun-Woo Chung, Seoul, KR;

Jiyoung Kim, Yongin-si, KR;

Yongchul Oh, Suwon-si, KR;

Sungkwan Choi, Hwaseong-si, KR;

Yoosang Hwang, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10876 (2013.01); H01L 27/10823 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.


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