The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
May. 28, 2009
Ethan H. Cannon, Essex Junction, VT (US);
David F. Heidel, Mahopac, NY (US);
K. Paul Muller, Wappingers Falls, NY (US);
Alicia Wang, Wappingers Falls, NY (US);
Ethan H. Cannon, Essex Junction, VT (US);
David F. Heidel, Mahopac, NY (US);
K. Paul Muller, Wappingers Falls, NY (US);
Alicia Wang, Wappingers Falls, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of 'in-line' connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art 'side-by-side' transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in “hardening” of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.