The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2015
Filed:
May. 22, 2014
Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;
Shintaro Yamamichi, Kanagawa, JP;
Kenta Ogawa, Kanagawa, JP;
Renesas Electronics Corporation, Tokyo, JP;
Abstract
This invention can reduce heat that is generated in a first semiconductor chip and transfers, to a second semiconductor chip through through-silicon vias. The first semiconductor chip has the first through-silicon vias. Each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n). The first semiconductor chip also has a first circuit formation area. A first circuit is formed in the first circuit formation area. The first circuit performs signal processing while communicating with the second semiconductor chip. In plan view, the first circuit formation area does not overlap with a through-silicon via area that is defined by coupling the outermost grid points arranged in m rows and n columns. In plan view, some of connection terminals are located between the first circuit formation area and the through-silicon via area.