The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Sep. 29, 2011
Applicants:

Hirotaka Ohno, Miyoshi, JP;

Takuya Kadoguchi, Toyota, JP;

Inventors:

Hirotaka Ohno, Miyoshi, JP;

Takuya Kadoguchi, Toyota, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 23/48 (2006.01); H01L 23/28 (2006.01); H01L 25/18 (2006.01); H01L 23/433 (2006.01); H01L 23/492 (2006.01); H01L 25/07 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/28 (2013.01); H01L 23/4334 (2013.01); H01L 23/492 (2013.01); H01L 25/072 (2013.01); H01L 25/18 (2013.01); H01L 23/3107 (2013.01); H01L 23/562 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/30107 (2013.01);
Abstract

This semiconductor device includes: a first metal plate; a plurality of semiconductor elements mounted on the first metal plate; a spacer that is connected to a surface on the opposite side to the surface where the plurality of semiconductor elements are mounted on the first metal plate; a second metal plate that is connected to a surface on the opposite side to the surface where the spacer is connected to the semiconductor elements; and an encapsulating resin between the first plate and the second plate that seals the plurality of semiconductor elements. Stress due to contraction that occurs in the encapsulating resin between the plurality of semiconductor elements is relaxed to a greater extent than stress due to contraction that occurs in the encapsulating resin in the locations other than the location between the plurality of semiconductor devices.


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