The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Oct. 29, 2014
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventors:

Yeon Uk Kim, Icheon-si, KR;

Jeong Tae Hwang, Icheon-si, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 17/16 (2006.01); G11C 17/18 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 17/18 (2013.01); G11C 5/148 (2013.01); G11C 17/16 (2013.01);
Abstract

Semiconductor devices are provided. The semiconductor device may include a control signal generator and a fuse array portion. The control signal generator may generate a power control signal, disable the power control signal to a ground voltage signal level during a power-up period, and enable the power control signal to a power supply voltage signal level from a moment that the power-up period terminates until a moment that a mode register set operation terminates. The fuse array portion may execute a boot-up operation while the power control signal is enabled. The fuse array portion may generate fuse data according to an electrical open/short state of a fuse. The fuse may be selected by a level combination of address signals during the boot-up operation.


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