Non-volatile memory devices and related operating methods

Abstract

Non-volatile memory devices and related methods are provided. The non-volatile memory devices include a memory cell array having a plurality of cell strings, each cell string including: a plurality of memory cells stacked in a direction perpendicular to a substrate, a ground selection transistor between the plurality of memory cells and the substrate, and a string selection transistor between the plurality of memory cells and a bit line; an address decoder coupled to the plurality of memory cells in the plurality of cell strings through word lines, to the string selection transistors in the plurality of cell strings through string selection lines, and to the ground selection transistors in the plurality of cell strings through a ground selection line; a read/write circuit coupled to the string selection transistors in the plurality of cell strings through the bit lines; and control logic configured to adjust a substrate voltage applied to the substrate such that threshold voltages of the ground selection transistors are higher than a predetermined level during read operations for at least one of the plurality of memory cells in the plurality of cell strings.