The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Aug. 18, 2010
Applicant:

Hiroaki Inoue, Tokyo, JP;

Inventor:

Hiroaki Inoue, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 2212/1028 (2013.01); Y02B 60/1225 (2013.01);
Abstract

There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (), and a small-area cache () having a type different from that of the cache (), the cache () and the cache () being independently supplied with source voltage; the cache () being operable at a voltage lower than the lower limit voltage at which the cache () is operable; a cache control unit () operating switchable controls between a first mode allowing only the cache () to operate, and a second mode allowing the cache () or the cache () to operate; and the cache () in the first mode operating to supply a voltage below the lower limit voltage at which the cache () is operable, while interrupting power supply to the cache ().


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