The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

May. 05, 2015
Applicant:

Topcon Positioning Systems, Inc., Livermore, CA (US);

Inventor:

Nikolay Vasilyuk, Moscow, RU;

Assignee:

Topcon Positioning Systems, Inc., Livermore, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 12/02 (2006.01); G11C 7/20 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/0619 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G06F 12/0802 (2013.01); G06F 3/0632 (2013.01); G06F 2003/0691 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/2022 (2013.01); G06F 2212/222 (2013.01); G06F 2212/305 (2013.01); G11C 7/20 (2013.01);
Abstract

An architecture of a NAND Flash memory module interface controller (NAND-controller) provides access to data stored in an external NAND Flash memory module, and a method of booting firmware. NAND-controller automatically boots firmware from the NAND Flash memory into primary RAM of a system-on-a chip used for GNSS receivers. NAND-controller has a first external interface to connect NAND Flash memory, a second external interface to set parameters of booting firmware, and two internal interfaces: a high-speed one (system interface) and a low-speed one (control interface) to be connected to two types of SoC internal busses. Data exchange between the CPU and NAND Flash memory is implemented using a static RAM buffer which is a part of the NAND-controller and available for reading and writing via high-speed interface. Parameters of the first external interface are set and current state of data exchange process is controlled by the CPU.


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