The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2015

Filed:

Dec. 10, 2012
Applicant:

Google Inc., Mountain View, CA (US);

Inventors:

Albert T. Borchers, Aptos, CA (US);

Benjamin S. Gelb, San Francisco, CA (US);

Thomas J. Norrie, Mountain View, CA (US);

Andrew T. Swing, Los Gatos, CA (US);

Assignee:

Google Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 3/038 (2013.01); G06F 19/00 (2011.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 3/064 (2013.01); G06F 3/0611 (2013.01); G06F 3/0638 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0665 (2013.01); G06F 3/0688 (2013.01); G06F 11/00 (2013.01); G06F 2212/7201 (2013.01);
Abstract

A data storage device includes multiple flash memory devices, where each of the flash memory devices is arranged into multiple blocks having multiple pages for storing data. The data storage device includes a memory controller operationally coupled with the flash memory devices. The memory controller is configured to receive a logical to physical address translation map from a host device, where a physical address includes a physical address for one of the flash memory devices. The memory controller is configured to store the logical to physical address translation map in a memory module on the memory controller, receive read commands directly from an application running on the host device, where the read commands include logical memory addresses that refer to the logical locations on the flash memory devices, and translate the logical addresses to physical memory addresses using the logical to physical address translation map.


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