The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2015
Filed:
Feb. 14, 2013
Sharp Kabushiki Kaisha, Osaka-shi, Osaka, JP;
Yoshimitsu Yamauchi, Osaka, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T, a source of a second transistor element T, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element Tand a drain of the second transistor element T. Each memory cell MC arranged in the same column includes the control node Nc connected to a shared first control line CL extending in a column direction, the first transistor element Thaving a source connected to a shared data signal line DL extending in the column direction, the second transistor element Thaving a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first control line CL, and the other end connected to a voltage supply line VL is provided with respect to each first control line CL.