The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Sep. 17, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Masachika Masuda, Tokorozawa, JP;

Toshihiko Usami, Akita, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 25/065 (2006.01); B82Y 10/00 (2011.01); G06K 19/077 (2006.01); G11C 5/02 (2006.01); H01L 23/31 (2006.01); H01L 23/50 (2006.01); H01L 23/538 (2006.01); H05K 1/11 (2006.01); H01L 25/07 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H05K 1/02 (2006.01); H05K 3/28 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); B82Y 10/00 (2013.01); G06K 19/077 (2013.01); G06K 19/07732 (2013.01); G11C 5/02 (2013.01); H01L 22/32 (2013.01); H01L 23/3121 (2013.01); H01L 23/3128 (2013.01); H01L 23/50 (2013.01); H01L 23/5388 (2013.01); H01L 24/06 (2013.01); H01L 24/49 (2013.01); H01L 25/0652 (2013.01); H01L 25/074 (2013.01); H05K 1/117 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49113 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/014 (2013.01); H01L 2924/01004 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01039 (2013.01); H01L 2924/01057 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/351 (2013.01); H05K 1/0268 (2013.01); H05K 3/284 (2013.01); H05K 2201/10159 (2013.01); H05K 2203/1572 (2013.01);
Abstract

A device featuring a substrate configured to include an upper surface and an opposing lower surface and, in parallel, a first and an opposing second peripheral edge, the first peripheral edge being smaller in length than the second peripheral edge, one or more semiconductor chip mounted over the upper surface of the substrate, a control semiconductor chip mounted over the upper surface of the substrate, a sealing resin covering the memory and control chips, and a plurality of external terminals provided over the lower surface of the substrate, the external terminals being arranged in a line along the first peripheral edge. The external terminals are used to fit the device to an electronic apparatus. The device may be a memory card having a stacked arrangement of two or more memory chips, and with the control chip being apart from or included in the stacked arrangement.


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