The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Sep. 17, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Khalil Hosseini, Weihmichl, DE;

Joachim Mahler, Regensburg, DE;

Franz-Peter Kalz, Regensburg, DE;

Joachim Voelter, Berlin, DE;

Ralf Wombacher, Burglengenfeld, DE;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/60 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/492 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/97 (2013.01); H01L 23/492 (2013.01); H01L 23/49575 (2013.01); H01L 23/49811 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.


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