The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Jan. 25, 2013
Applicant:

Novachips Canada Inc., Ottawa, CA;

Inventor:

Byoung Jin Choi, Ottawa, CA;

Assignee:

NovaChips Canada Inc., Ottawa, Ontario, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); G11C 5/04 (2006.01); H05K 1/02 (2006.01); H01L 25/065 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/48 (2013.01); G11C 5/04 (2013.01); G11C 5/063 (2013.01); H01L 21/50 (2013.01); H01L 25/0652 (2013.01); H05K 1/0243 (2013.01); H01L 2224/16225 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H05K 1/181 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10545 (2013.01);
Abstract

A method, system and apparatus for connecting multiple memory device dies-to a substratewhich requires no trace between dies. A first embodiment assigns the connections of a memory device dieto be matched with other memory device dies-when mounted in staggered formation on the both sides of a substrate. The result is a daisy chained array connecting multiple integrated circuits with reduced capacitive loading. The capacitive loadings on the busesbetween memory device diesare reduced. The number of viasis reduced because two stubs on the both sides of the substrate share one via. Another embodiment FIG.arranges the dies in a closed loop.


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