The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Mar. 14, 2014
Applicants:

Karl D. Hobart, Alexandria, VA (US);

Marko J. Tadjer, Springfield, VA (US);

Tatyana I. Feygelson, Springfield, VA (US);

Bradford B. Pate, Arlington, VA (US);

Travis J. Anderson, Alexandria, VA (US);

Inventors:

Karl D. Hobart, Alexandria, VA (US);

Marko J. Tadjer, Springfield, VA (US);

Tatyana I. Feygelson, Springfield, VA (US);

Bradford B. Pate, Arlington, VA (US);

Travis J. Anderson, Alexandria, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/20 (2006.01); H01L 23/373 (2006.01); H01L 29/778 (2006.01); H01L 29/16 (2006.01); H01L 23/367 (2006.01); H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3732 (2013.01); H01L 23/367 (2013.01); H01L 23/481 (2013.01); H01L 29/1602 (2013.01); H01L 29/7786 (2013.01); H01L 21/02381 (2013.01); H01L 21/02527 (2013.01); H01L 21/02645 (2013.01); H01L 23/3677 (2013.01); H01L 29/0657 (2013.01); H01L 29/2003 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An array of through-silicon vias (TSVs) are formed in a silicone substrate. The vias can be tapered such that the diameter of the via at the surface of the substrate is larger than the diameter of the via at its bottom, with the diameter varying continuously along its depth. After the via is formed, it is seeded with a thin layer of nanocrystalline diamond (NCD) particles, and a NCD film is grown on the bottom and along the sidewalls of the via. The presence of the diamond-filled vias provides improved thermal management to semiconductor devices formed on the silicon substrate.


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