The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9159618 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 13, 2015

Filed:

Oct. 16, 2012
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventors:

Kenichiro Hijioka, Kawasaki, JP;

Naoya Inoue, Kawasaki, JP;

Yoshihiro Hayashi, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 21/768 (2006.01); H01L 27/02 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 27/0207 (2013.01); H01L 27/10814 (2013.01); H01L 27/10852 (2013.01); H01L 27/10885 (2013.01); H01L 27/10891 (2013.01); H01L 27/10894 (2013.01); H01L 28/91 (2013.01); H01L 21/76807 (2013.01); H01L 21/76816 (2013.01);
Abstract

A semiconductor device includes a substrate, an interlayer insulation layer, first transistors, a multilayered interconnect layer, capacitance devices, metal interconnects, and first contacts. Interlayer insulation films are disposed over the substrate. The first transistors are disposed to the substrate and buried in the interlayer insulation layer. The first transistor has at least a gate electrode and a diffusion electrode. A multilayered interconnect layer is disposed over the interlayer insulation film. The capacitance devices are disposed in the multilayered interconnect layer. The metal interconnect is in contact with the upper surface of the gate electrode and buried in the interlayer insulation layer. The first contact is coupled to the diffusion layer of the first transistor and buried in the interlayer insulation layer. The metal interconnect includes a material identical with that of the first contact.


Find Patent Forward Citations

Hijioka, Kenichiro. (2015). Semiconductor device with contacts and metal interconnects and method of manufacturing the semiconductor device (U.S. Patent No. 9159618). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9159618

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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