The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Dec. 15, 2006
Applicants:

Chungho Lee, Sunnyvale, CA (US);

Wei Zheng, Santa Clara, CA (US);

Chi Chang, Saratoga, CA (US);

Unsoon Kim, San Jose, CA (US);

Hiroyuki Kinoshita, San Jose, CA (US);

Inventors:

Chungho Lee, Sunnyvale, CA (US);

Wei Zheng, Santa Clara, CA (US);

Chi Chang, Saratoga, CA (US);

Unsoon Kim, San Jose, CA (US);

Hiroyuki Kinoshita, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 27/115 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28282 (2013.01); H01L 27/115 (2013.01); H01L 27/11521 (2013.01); H01L 27/11568 (2013.01); H01L 29/1037 (2013.01); H01L 29/1083 (2013.01); H01L 29/42332 (2013.01); H01L 29/42348 (2013.01); H01L 29/66537 (2013.01); H01L 29/7887 (2013.01); H01L 29/7923 (2013.01);
Abstract

Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.


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