The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Jun. 25, 2013
Applicant:

Jeon-taek Im, Anseong-Si, KR;

Inventor:

Jeon-Taek Im, Anseong-Si, KR;

Assignee:

Samsung Electronics, Co., Ltd., Yeongtong-Gu, Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 16/26 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G11C 16/06 (2006.01); G06F 12/06 (2006.01); G06F 12/08 (2006.01); G06F 12/02 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 5/02 (2013.01); G11C 5/04 (2013.01); G11C 7/109 (2013.01); G11C 7/1042 (2013.01); G11C 7/1051 (2013.01); G11C 7/1063 (2013.01); G11C 7/1078 (2013.01); G11C 16/06 (2013.01); G06F 12/0246 (2013.01); G06F 12/0623 (2013.01); G06F 12/0804 (2013.01);
Abstract

A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.


Find Patent Forward Citations

Loading…