The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2015
Filed:
Jun. 03, 2014
Applicant:
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Inventor:
Jong Ho Jung, Icheon-si, KR;
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G11C 7/22 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/222 (2013.01); G11C 7/1066 (2013.01); G11C 7/22 (2013.01); H03L 7/0805 (2013.01); H03L 7/0816 (2013.01); G11C 2207/2272 (2013.01);
Abstract
A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.