The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Oct. 28, 2010
Applicants:

Hiromi Enomoto, Osaka, JP;

Shinsuke Yokonuma, Osaka, JP;

Yoji Inui, Osaka, JP;

Toshihiko Miyashita, Osaka, JP;

Hiroyuki Kitamura, Osaka, JP;

Inventors:

Hiromi Enomoto, Osaka, JP;

Shinsuke Yokonuma, Osaka, JP;

Yoji Inui, Osaka, JP;

Toshihiko Miyashita, Osaka, JP;

Hiroyuki Kitamura, Osaka, JP;

Assignee:

Sharp Kabushiki Kaisha, Osaka-shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3677 (2013.01);
Abstract

The present invention includes, in addition to transistors each (Mm,n) provided at the intersection of a gate bus line (GLn) with a data bus line (DLm): block potential applying transistors (DMn) connected to respective ends of gate bus lines (GLn) which ends are not connected to a gate driver (); a potential supply line (VLL) connected to the gate bus lines (GLn) via the block potential applying transistors (DMn); and a blocking signal supplying section () for, immediately after the gate driver () supplies a first conduction signal for bringing the transistors (Mm,n) into conduction, supplying to the block potential applying transistors (DMn), a second conduction signal for bringing the block potential applying transistors (DMn) into conduction.


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