The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Jan. 03, 2014
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, Guangdong, CN;

Inventors:

Xiaojiang Yu, Guangdong, CN;

Changyeh Lee, Guangdong, CN;

Tzuchieh Lai, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G02F 1/133 (2006.01); G02F 1/1345 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3607 (2013.01); G02F 1/13306 (2013.01); G02F 1/13454 (2013.01); G09G 3/3648 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/027 (2013.01); G09G 2310/0248 (2013.01); G09G 2320/0242 (2013.01); G09G 2320/0252 (2013.01);
Abstract

The present invention relates to a GOA circuit for liquid crystal displaying and a display device. The GOA circuit includes a plurality of cascaded GOA units and the nth-stage GOA unit includes a pull-up part (), a key pull-down part (), a pull-down holding part (), a pull-up control part (), and a boost capacitor (Cb). In operation, a nth-stage clock signal (CK(n)) and first and second clock signals (LCand LC) are inputted. The frequencies of the first clock signal (LC) and the second clock signal (LC) are lower than the nth clock signal (CK(n)). The first clock signal (LC) charging a first circuit point (P) and the second clock signal (LC) charging a second circuit point (K) are alternately carried out. The present invention also provides a corresponding display device. The GOA circuit of the present invention precisely controls the voltage of the gate Q(n) that affects charging of a horizontal scan line by means of the low frequency clock signal and the high frequency clock signal, so as to ensure a stable output of the GOA charging signal.


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