The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Mar. 12, 2013
Applicants:

Ken Keon Shin, Seongnam-Si, KR;

Hoi Jin Lee, Seoul, KR;

Gun OK Jung, Yongin-Si, KR;

Min Su Kim, Hwaseong-Si, KR;

Inventors:

Ken Keon Shin, Seongnam-Si, KR;

Hoi Jin Lee, Seoul, KR;

Gun Ok Jung, Yongin-Si, KR;

Min Su Kim, Hwaseong-Si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); G06F 1/32 (2006.01); H03K 19/00 (2006.01); H03K 19/096 (2006.01);
U.S. Cl.
CPC ...
G06F 1/32 (2013.01); G06F 1/04 (2013.01); H03K 19/0008 (2013.01); H03K 19/0963 (2013.01);
Abstract

A domino logic circuit includes a pre-charge circuit pre-charging a first dynamic node in response to a clock signal, a first logic network determining a logic level of the first dynamic node in response to first data signals, an inverter receiving the clock signal, a discharge circuit discharging a second dynamic node in response to an output signal of the inverter, and a second logic network determining a logic level of the second dynamic node in response to at least one second data signal and an output signal of the first dynamic node.


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