The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2015
Filed:
Nov. 25, 2013
Lsi Corporation, San Jose, CA (US);
Manjunatha Gowda, San Jose, CA (US);
Ramnath Venkatraman, San Jose, CA (US);
Thai M. Nguyen, San Jose, CA (US);
Hai H. Tan, Fremont, CA (US);
Prasad Subbarao, San Jose, CA (US);
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD., Singapore, SG;
Abstract
In one embodiment, an integrated circuit (IC) device includes a first logic block having performance characteristics, a first critical path monitor (CPM) configured to monitor the performance characteristics of the first logic block, and a first CPM envelope circuit enveloping the first CPM. The first logic block is configured to operate in at least one of a first functional mode and a first scan mode. The first CPM is adapted to operate in at least one of a second functional mode and a second scan mode. The first and second functional modes use higher clock frequencies, respectively, than the first and second scan modes. The first CPM envelope circuit comprises a clock-gate circuit adapted to allow the IC device to operate in a mixed mode, wherein the first CPM operates in the second functional mode while the first logic block operates in the first scan mode.