The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2015

Filed:

Jun. 24, 2009
Applicants:

Walter B. Meinel, Tucson, AZ (US);

Kalin V. Lazarov, Tucson, AZ (US);

Brian E. Goodlin, Plano, TX (US);

Inventors:

Walter B. Meinel, Tucson, AZ (US);

Kalin V. Lazarov, Tucson, AZ (US);

Brian E. Goodlin, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01J 5/12 (2006.01); B81C 1/00 (2006.01); G01J 5/02 (2006.01);
U.S. Cl.
CPC ...
G01J 5/12 (2013.01); B81C 1/00047 (2013.01); G01J 5/02 (2013.01); G01J 5/024 (2013.01); G01J 5/0225 (2013.01); B81B 2201/0292 (2013.01);
Abstract

A semiconductor device includes a semiconductor layer () and a dielectric stack () on the semiconductor layer. A plurality of etchant openings (-. . . ) are formed through the dielectric stack () for passage of etchant for etching a plurality of overlapping sub-cavities (-. . . ), respectively. The etchant is introduced through the etchant openings to etch a composite cavity () in the semiconductor layer by simultaneously etching the plurality of overlapping sub-cavities into the semiconductor layer.


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