The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Jan. 21, 2010
Applicants:

Junya Maruyama, Ebina, JP;

Tomoyuki Aoki, Atsugi, JP;

Inventors:

Junya Maruyama, Ebina, JP;

Tomoyuki Aoki, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/30 (2006.01); H05K 3/20 (2006.01); H05K 3/24 (2006.01);
U.S. Cl.
CPC ...
H05K 3/205 (2013.01); H01L 2224/11 (2013.01); H05K 3/245 (2013.01); H05K 2203/0117 (2013.01); Y10T 29/49016 (2015.01); Y10T 29/49018 (2015.01); Y10T 29/49117 (2015.01); Y10T 29/49144 (2015.01); Y10T 29/49155 (2015.01); Y10T 29/49224 (2015.01);
Abstract

A manufacturing method of a wiring board and a semiconductor device at low cost and by a simple process, without performing complicated steps many times is proposed. Furthermore, a manufacturing method of a wiring board at low cost and with fewer adverse effects on the environment, and a manufacturing method of a semiconductor device using the wiring board are proposed. A pattern of a conductive material is formed over a first substrate, a conductive film is formed over the pattern by an electrolytic plating process, the pattern and the conductive film are separated, an IC chip including at least one thin film transistor is formed over a second substrate, and the conductive film is electrically connected to the IC chip.


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