The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Jun. 06, 2014
Applicant:

Phison Electronics Corp., Miaoli, TW;

Inventors:

Yun-Chieh Chen, Miaoli County, TW;

Shih-Kung Lin, Hsinchu County, TW;

Ta-Chuan Wei, Miaoli County, TW;

Hsiang-Hsiung Yu, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/14 (2006.01); H01L 23/522 (2006.01); H05K 1/02 (2006.01); G11C 5/02 (2006.01); H05K 1/11 (2006.01); H01R 13/66 (2006.01); H01R 13/6581 (2011.01);
U.S. Cl.
CPC ...
H05K 1/0219 (2013.01); G11C 5/02 (2013.01); H01L 23/14 (2013.01); H01L 23/5225 (2013.01); H01R 13/6581 (2013.01); H01R 13/665 (2013.01); H05K 1/0224 (2013.01); H05K 1/0225 (2013.01); H05K 1/0227 (2013.01); H05K 1/0298 (2013.01); H05K 1/111 (2013.01); H05K 2201/0723 (2013.01);
Abstract

A multi-layer printed circuit board structure, a connector module and a memory storage device are provided. The multi-layer printed circuit board structure includes a first layout layer and a second layout layer. The first layout layer includes a shielding element and at least one pad. The shielding element provides the grounding voltage. The second layout layer is disposed corresponding to the first layout layer and includes at least one wire, and one end of each wire is coupled to one of the pads. A predefined proportion of the wire is covered by a projection plane of the shielding element projected on the second layout layer.


Find Patent Forward Citations

Loading…