The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Mar. 13, 2014
Applicant:

Integrated Device Technology, Inc., San Jose, CA (US);

Inventors:

Arnaud Biallais, Goneville sur Mer, FR;

Fatima Ghanem, Caen, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/12 (2006.01); H03M 1/08 (2006.01); H03M 1/10 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0609 (2013.01); H03M 1/0607 (2013.01); H03M 1/08 (2013.01); H03M 1/109 (2013.01); H03M 1/121 (2013.01); H03M 1/1215 (2013.01);
Abstract

The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC includes determining signs of the signals and outputting corresponding values by the counting unit. The values are further compared and integrated to estimate the offset error. The method for estimating a gain error in a time-interleaved ADC includes determining the absolute values of the signals and comparing the absolute values with a predetermined threshold value. The comparison results are further integrated to estimate the gain error.


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