The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Apr. 27, 2014
Applicants:
Reecha Jajodia, Noida, IN;
Gaurav Goyal, Dehradun, IN;
Inventors:
Reecha Jajodia, Noida, IN;
Gaurav Goyal, Dehradun, IN;
Assignee:
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/00 (2006.01); H03K 19/00 (2006.01); H03K 19/177 (2006.01); H03K 19/173 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17724 (2013.01); H03K 19/00392 (2013.01); H03K 19/1736 (2013.01); H03K 19/17748 (2013.01); H03K 19/17764 (2013.01);
Abstract
Spare gate cells for inclusion in an integrated circuit have multiple inputs and outputs and are capable of selectively performing, concurrently, multiple logic functions on signals appearing at the inputs. Selection of required logic functions depends on the connections of at least one of the inputs of the spare cell. One of the outputs is fed back to an input of the spare gate cell to provide certain functionality while other outputs are set to a fixed logical value. The spare gate cell may be configured to perform NOR, OR and inverter operations on inputs simultaneously.