The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Aug. 27, 2010
Applicants:

OK Hyun Nam, Seoul, KR;

Dong Hun Lee, Seoul, KR;

Geun Ho Yoo, Incheon, KR;

Inventors:

Ok Hyun Nam, Seoul, KR;

Dong Hun Lee, Seoul, KR;

Geun Ho Yoo, Incheon, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 33/16 (2010.01); H01L 29/20 (2006.01); H01L 31/0304 (2006.01); H01L 31/18 (2006.01); H01L 33/12 (2010.01); H01L 33/20 (2010.01); H01L 33/00 (2010.01); H01L 33/22 (2010.01); H01S 5/02 (2006.01); H01S 5/32 (2006.01); H01S 5/323 (2006.01);
U.S. Cl.
CPC ...
H01L 33/16 (2013.01); H01L 29/2003 (2013.01); H01L 31/0304 (2013.01); H01L 31/1856 (2013.01); H01L 33/007 (2013.01); H01L 33/12 (2013.01); H01L 33/0062 (2013.01); H01L 33/20 (2013.01); H01L 33/22 (2013.01); H01S 5/0213 (2013.01); H01S 5/3202 (2013.01); H01S 5/32341 (2013.01); H01S 2304/12 (2013.01); Y02E 10/544 (2013.01);
Abstract

Provided are a high-quality non-polar/semi-polar semiconductor device having reduced defect density of a nitride semiconductor layer and improved internal quantum efficiency and light extraction efficiency, and a manufacturing method thereof. The method for manufacturing a semiconductor device is to form a template layer and a semiconductor device structure on a sapphire, SiC or Si substrate having a crystal plane for a growth of a non-polar or semi-polar nitride semiconductor layer. The manufacturing method includes: forming a nitride semiconductor layer on the substrate; performing a porous surface modification such that the nitride semiconductor layer has pores; forming the template layer by re-growing a nitride semiconductor layer on the surface-modified nitride semiconductor layer; and forming the semiconductor device structure on the template layer.


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