The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Oct. 20, 2014
Applicant:
X-fab Semiconductor Foundries Ag, Erfurt, DE;
Inventors:
Daniel Gaebler, Apolda OT Sulzbach, DE;
Wolfgang Einbrodt, Erfurt, DE;
Assignee:
X-FAB SEMICONDUCTOR FOUNDRIES AG, Erfurt, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0224 (2006.01); H01L 31/0232 (2014.01); H01L 27/146 (2006.01); H01L 31/02 (2006.01); H01L 31/028 (2006.01); H01L 31/113 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 31/02327 (2013.01); H01L 27/14618 (2013.01); H01L 31/02005 (2013.01); H01L 31/028 (2013.01); H01L 31/022408 (2013.01); H01L 31/1136 (2013.01); H01L 21/823475 (2013.01); H01L 2924/0002 (2013.01);
Abstract
A window opening in a semiconductor component is produced on the basis of a gate structure which serves as an efficient etch resist layer in order to reliably etch an insulation layer stack without exposing the photosensitive semiconductor area. The polysilicon in the gate structure is then removed on the basis of an established gate etching process, with the gate insulation layer preserving the integrity of the photosensitive semiconductor material.