The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

May. 23, 2013
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Klaus Elian, Alteglofsheim, DE;

Helmut Wietschorke, Laberweinting, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/56 (2006.01); H01L 29/84 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/84 (2013.01); H01L 24/97 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/48465 (2013.01);
Abstract

Techniques for covering open-cavity integrated-circuit packages in a batch process are disclosed. In an example method, a plurality of open-cavity packages are molded on a single batch leadframe or substrate, each open-cavity package comprising a floor and a plurality of walls arranged around the floor to form a cavity, each of said the walls having a bottom end adjoining said floor and having a top side opposite the bottom end. At least one semiconductor device is attached to the floor and within the cavity of each of the open-cavity packages, and a single flexible membrane is affixed to the top sides of the walls of the plurality of open-cavity packages, so as to substantially cover all of the cavities. The flexible membrane is then severed, between the packages.


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