The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Oct. 15, 2014
Applicant:

Abb Schweiz Ag, Baden, CH;

Inventor:

Christoph von Arx, Olten, CH;

Assignee:

ABB SCHWEIZ AG, Baden, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/43 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7396 (2013.01); H01L 29/0615 (2013.01); H01L 29/0804 (2013.01); H01L 29/404 (2013.01); H01L 29/408 (2013.01); H01L 29/41775 (2013.01); H01L 29/435 (2013.01); H01L 29/4916 (2013.01);
Abstract

An IGBT is disclosed with a high emitter-gate capacitance, wherein an active cell region can include plural emitter and gate regions. A termination edge region can include a varied lateral doping region VLD. Each gate polysilicon layer can be arranged at a surface of the semiconductor substrate in the gate regions, separated from the semiconductor substrate by a first insulating layer. A first SIPOS layer and a covering second insulating layer overlie at least portions of the gate polysilicon layer. In a central area, the gate polysilicon layer is in electrical contact with the overlying first SIPOS layer whereas, in a peripheral area, the gate polysilicon layer is electrically separated from the overlying first SIPOS layer. A substrate surface at the VLD region is in electrical contact with a second SIPOS layer, and an increased gate-emitter capacitance may be achieved by slightly modifying etch masks during manufacturing.


Find Patent Forward Citations

Loading…