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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9153593 B1

PDFFull Text
Date of Patent:
Oct. 06, 2015

Filed:

Jul. 25, 2014

Nonvolatile memory device having single-layer gate, method of operating the same, and memory cell array thereof

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Hyun Min Song, Chungcheongbuk-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T Group LLP

Primary Examiner:

Vu Le

Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/115 (2006.01); G11C 7/00 (2006.01); H01L 29/78 (2006.01); H01L 49/02 (2006.01); H01L 29/861 (2006.01); H01L 29/423 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/115 (2013.01); G11C 7/00 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 27/11526 (2013.01); H01L 28/40 (2013.01); H01L 29/4232 (2013.01); H01L 29/78 (2013.01); H01L 29/861 (2013.01);
Abstract

A nonvolatile memory device includes a single-layer gate, a first area, and a second area. The first area includes a first well region, a first contact region arranged in the first well region, and source and drain regions arranged at both sides of the single-layer gate in the first well region. The second area includes a second well region, a second contact region arranged to overlap a part of the single-layer gate in the second well region, and a third contact region arranged in the second well region.

Find Patent Forward Citations

Song, Hyun. (2015). Nonvolatile memory device having single-layer gate, method of operating the same, and memory cell array thereof (U.S. Patent No. 9153593). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9153593

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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