The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Feb. 25, 2007
Applicants:

Jin-yuan Lee, Hsin-Chu, TW;

Ying-chih Chen, Tainan, TW;

Mou-shiung Lin, Hsinchu, TW;

Inventors:

Jin-Yuan Lee, Hsin-Chu, TW;

Ying-Chih Chen, Tainan, TW;

Mou-Shiung Lin, Hsinchu, TW;

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05171 (2013.01); H01L 2224/05187 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05556 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05644 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/4807 (2013.01); H01L 2224/48453 (2013.01); H01L 2224/48463 (2013.01); H01L 2224/48599 (2013.01); H01L 2224/48624 (2013.01); H01L 2224/48644 (2013.01); H01L 2224/854 (2013.01); H01L 2224/85424 (2013.01); H01L 2224/85444 (2013.01); H01L 2224/85447 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/014 (2013.01); H01L 2924/0105 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01007 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01024 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01078 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/14 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01);
Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.


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