The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Feb. 27, 2014
Altera Corporation, San Jose, CA (US);
Aron Joseph Roth, North York, CA;
Michael Chan, Scarborough, CA;
Jeffrey Christopher Chromczak, Brownsville, CA;
Altera Corporation, San Jose, CA (US);
Abstract
An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may be associated with a given tile type, and each tile type may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a given tile, which is sometimes also referred to as wire twisting. Wire twists may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires. At the same time, the twist region height (i.e., the region in the tile in which wires are twisted) may be reduced compared to conventional interconnect circuitry.