The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Jun. 17, 2014
Heribert Weber, Nuertingen, DE;
Hartmut Kueppers, Reutlingen, DE;
Jochen Reinmuth, Reutlingen, DE;
Neil Davies, Sonnenbuehl-Genkingen, DE;
Jens Frey, Filderstadt, DE;
Heribert Weber, Nuertingen, DE;
Hartmut Kueppers, Reutlingen, DE;
Jochen Reinmuth, Reutlingen, DE;
Neil Davies, Sonnenbuehl-Genkingen, DE;
Jens Frey, Filderstadt, DE;
ROBERT BOSCH GMBH, Stuttgart, DE;
Abstract
In an ASIC element, vias are integrated into the CMOS processing of an ASIC substrate. The ASIC element includes an active front side in which the circuit functions are implemented. The at least one via is intended to establish an electrical connection between the active front side and the rear side of the element. The front side of the via is defined by at least one front-side trench which is completely filled, and the rear side is defined by at least one rear-side trench which is not completely filled. The rear-side trench opens into the filled front-side trench.