The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Apr. 22, 2011
Applicants:

Mamoru Terai, Tokyo, JP;

Seiki Hiramatsu, Tokyo, JP;

Tatsuo Ota, Tokyo, JP;

Hiroya Ikuta, Tokyo, JP;

Takashi Nishimura, Tokyo, JP;

Inventors:

Mamoru Terai, Tokyo, JP;

Seiki Hiramatsu, Tokyo, JP;

Tatsuo Ota, Tokyo, JP;

Hiroya Ikuta, Tokyo, JP;

Takashi Nishimura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H01L 29/16 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/28 (2013.01); H01L 25/07 (2013.01); H01L 25/18 (2013.01); H01L 29/16 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/4903 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/19107 (2013.01);
Abstract

A semiconductor device includes: a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface; semiconductor elements affixed to the surface of the front-surface electrode pattern opposite the insulating substrate; and a sealing resin member which covers the semiconductor element and the semiconductor-element substrate, wherein at a position of the front-surface electrode pattern where the position has potential equivalent to that of the front-surface electrode pattern at a position where a semiconductor element is bonded, an insulating terminal table formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other are provided, and wiring from the semiconductor element to the outside is led out via the relay terminal.


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