The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Mar. 13, 2012
Applicants:

Shunsaku Muraoka, Osaka, JP;

Satoru Mitani, Osaka, JP;

Takeshi Takagi, Kyoto, JP;

Inventors:

Shunsaku Muraoka, Osaka, JP;

Satoru Mitani, Osaka, JP;

Takeshi Takagi, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); H01L 27/10 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/0007 (2013.01); H01L 27/101 (2013.01); H01L 27/2436 (2013.01); H01L 45/04 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/32 (2013.01); G11C 2213/79 (2013.01);
Abstract

A method for driving a nonvolatile memory element includes: a writing step of changing a variable resistance layer to a low resistance state, by applying a writing voltage pulse having a first polarity; and an erasing step of changing the variable resistance layer to a high resistance state, by applying an erasing voltage pulse having a second polarity different from the first polarity, wherein in the writing step, a first input and output terminal of a field effect transistor is a source terminal of the transistor, and when a pulse width of the writing voltage pulse is PWLR and a pulse width of the erasing voltage pulse is PWHR, PWLR and PWHR satisfy a relationship of PWLR<PWHR.


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