The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2015
Filed:
Jul. 12, 2012
Nakaba Kaiwa, Tokyo, JP;
Yoshinori Matsui, Tokyo, JP;
Nakaba Kaiwa, Tokyo, JP;
Yoshinori Matsui, Tokyo, JP;
PS4 Luxco S.a.r.l., Luxembourg, LU;
Abstract
A semiconductor memory device includes a memory cell array section including a plurality of memory cell arrays, a peripheral circuit section, and an internal bus connecting the plurality of memory cell arrays and the peripheral circuit section. The peripheral circuit section includes external input/output buffers, and bus interface circuits. The bus interface circuits execute conversion between data inputted/outputted in parallel to/from the memory cell arrays through the internal bus and data inputted/outputted in serial through the plurality of external input/output buffers. The bus interface circuits are densely arranged between the internal bus and the input/output buffers, so that a width dof the area of the plurality of bus interface circuits being arranged is narrower than a width dof the area of the external input/output buffers being arranged and a bus width maximum value dof the internal bus.