The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Sep. 06, 2013
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Michael B. Galles, Los Altos, CA (US);

Hemant M. Vinchure, San Jose, CA (US);

Assignee:

CISCO TECHNOLOGY, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/38 (2006.01); H04L 29/12 (2006.01);
U.S. Cl.
CPC ...
G06F 13/385 (2013.01); G06F 13/409 (2013.01); G06F 13/4022 (2013.01); H04L 29/12367 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0058 (2013.01); G06F 2213/3808 (2013.01);
Abstract

Methods and systems are disclosed herein for providing a universal PCIe port. The same port can be configured to accept a PCIe component as a host or an endpoint (device) symmetrically. The PCIe port can be connected to the host interface or the root complex interface if the PCIe connection is to be configured as a host or an endpoint, respectively. A virtual topology can be provided for a host that associates the host with corresponding endpoints. A mapping between virtual addresses of the corresponding endpoints in the virtual topology and local addresses of the corresponding endpoints is provided.


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