The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2015

Filed:

Nov. 04, 2008
Applicants:

Jian LI, Austin, TX (US);

Ramakrishnan Rajamony, Austin, TX (US);

William E. Speight, Austin, TX (US);

Xiaoxia Wu, State College, PA (US);

Lixin Zhang, Austin, TX (US);

Inventors:

Jian Li, Austin, TX (US);

Ramakrishnan Rajamony, Austin, TX (US);

William E. Speight, Austin, TX (US);

Xiaoxia Wu, State College, PA (US);

Lixin Zhang, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/08 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0897 (2013.01); G06F 12/0811 (2013.01); G06F 12/0846 (2013.01); G06F 12/0848 (2013.01); G06F 12/123 (2013.01); G06F 2212/225 (2013.01); G06F 2212/271 (2013.01);
Abstract

In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.


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